Modular Minimization of Finite State Machines

This work presents a modular technique for minimizing a nite state machine FSM while preserving its equivalence to the original system Being modular the minimization technique should consume less time and space Preserving equivalence the resulting minimized model can be employed in both temporal logic model checking and sequential equivalence checking thus reducing their time and space consumption Most systems have a natural modular structure and we suggest using this structure in the minimization of their model The complexity of minimizing a single module can be exponentially smaller than that of minimizing the entire system The actual reduction in complexity depends on the module connectivity to the other parts of the system Thus the method has great potential This modular algorithm has been implemented on an Intel system in Intel Haifa and it has been tested on real hardware designs